1. Field of the Invention
The present invention relates to wireless communication systems, and more specifically, to an implementation of a software router for routing signals among various channels within and between data links.
2. Description of the Related Art
Analog wireless calls, carrying, for example, 64 kilobits/sec of Pulse Code Modulated (PCM) data, require an end-to-end dedicated circuit switched path for the entire duration of the call. This switched path is typically between communication channels, either within a communication link, or between different communication links. For the purposes of discussion, a communication link will be assumed to contain 10 communication channels, although other links with more or less channels are possible.
This dedicated circuit switched path has conventionally been provided via a hardware router or another hardware-based implementation for performance and voice quality reasons. The router may be located in, for example, a base station, although other locations within a wireless communication system are possible depending on a configuration of the system. However, the recent advent of software defined radios have necessitated other implementations of these routers.
“Software defined radios” refer to a radio whose personality may be changed to either digital or analog via software. An example of such a radio is one capable of operating using either an analog protocol or a digital protocol, such as TDMA. The introduction of such software defined radios has made it necessary to provide some segments of the dedicated circuit switched path for an analog call via software.
FIG. 1 shows a block diagram of an Analog/PCM software circuit switching router 100. In the implementation shown, the router supports two links 10 and 20, each having 10 channels, for a total of 20 channels. Shown in FIG. 2 are possible exemplary mappings of various channels in each link. In general, a channel on one link may be connected to a channel on another link, such a channel 1 on link 10 connected to channel 10 on link 20 as shown. Alternately, a channel may be connected to another channel on the same link, such as channels 8 and 10 on link 10 or channels 3 and 6 on link 20. Another possible configuration is routing a channel to itself, as shown for channel 5 on link 10 and channel 1 on link 20. All of these channel mappings are determined by routing software implemented in a processor or computing unit, such as the MPC860 processor manufactured by Motorola, Inc.
Because these channels are carrying analog/PCM voice data, the software router 100 needs to move data serially from its source to destination channel with no protocol superimposition, or other interruption or delay of the data. Channels which need to move data (e.g., PCM data and other data which must remain continuous) in such an uninterrupted manner will be termed “analog channels,” which are distinct from, e.g., “digital channels” which carry packetized data in a discontinuous manner. To maintain this uninterrupted data, a “transparent mode” protocol is used to operate these analog channels. Transparent mode provides a clear channel on which a Serial Communication Controller (SCC) of the processor implementing the routing software does not perform any bit-level manipulation. Such modes are necessarily processor-dependent in their implementation, and it is envisioned that other processors besides the MPC860 processor will operate in a similar mode when running a software router.
The two links 10 and 20 of the router 100 have an 8 kHz Frame Sync pulse in the following example. This means that a byte of data is transmitted/received every 125 microseconds on these links. The data is received by the SCC device of the MPC860 processor, where it gets buffered. Once the specified number of bytes are buffered for the transparent mode channel, the SCC generates an interrupt to the main core of the MPC860 processor for further processing, e.g., data routing to establish circuit switching. In one possible implementation, each transparent mode channel is configured to buffer 64 bytes prior to transferring the data to a corresponding destination channel. Thus, each transparent channel generates an interrupt every 8 milliseconds, because 125 microseconds*64 bytes=8 milliseconds. The number of bytes to buffer may be chosen according to a compromise between performance and quality. A smaller number of buffered bytes would cause performance degradation due to higher interrupt activity and consequently higher context switch overhead. A larger number of buffered bytes, on the other hand, would result in poor voice quality due to echoing on the line.
Since in the above example, each of the transparent channels of each link is configured to buffer 64 bytes, 20 interrupts (one for each channel) will be generated by the SCC every 8 milliseconds. To achieve acceptable circuit switching, the 64 bytes received on each channel needs to be transmitted to its corresponding mapped destination channel as illustrated, for example, in FIG. 2. This conventional, one interrupt per channel scheme results in the following processor utilization due solely to the software router.
Over a time period of 1 second (=1000 milliseconds), the number of interrupts (NUM) generated is 2500 (=10 interrupts per link every 8 milliseconds). The software router has an overhead associated with each interrupt, which is 54 microseconds in this example. Further, there is a latency of 50 microseconds associated with each channel's interrupt to route the 64 bytes per channel. Hence, the percentage of processor utilization of just the software router may be expressed as follows:                                                                         CPU                ⁢                                                                   ⁢                Utilization                            =                            ⁢                                                                    (                                                                  (                                                  Overhead                          +                          Latency                                                )                                            *                      NUM                                        )                                    /                  Time                                ⁢                                                                   ⁢                Period                                                                                        =                            ⁢                                                (                                                            (                                                                        54                          ⁢                                                                                                           ⁢                          microseconds                                                +                                                  50                          ⁢                                                                                                           ⁢                          microseconds                                                                    )                                        *                    2500                                    )                                /                                                                                                      ⁢                              1000                ⁢                                                                   ⁢                milliseconds                                                                                        =                            ⁢                              0.265                ⁢                                                                   ⁢                                  (                                      26.5                    ⁢                    %                                    )                                                                                        (        1        )            Thus, a conventional software router between two links of 10 analog channels in the example above may utilize over one quarter of a processor's resources. This is a significant amount of load, considering that the processor where this router resides, has to support numerous other time critical tasks.